1. Field of the Invention
The present invention relates to a high-speed semiconductor integrated circuit device, and more particularly to improvement of an internal wiring structure which is used for semiconductor integrated circuit chips to enable a high-speed operation.
2. Description of the Related Art
With the recent increasing need for high-speed logic performance of digital systems, such as an optical communication apparatus, a supercomputer, etc., the technique for efficiently processing high-speed signals has become indispensable. As basic devices for providing the internal circuits of these electronic devices, an HBT, an HEMT, a GaAs-MESFET, a Si-bipolar transistor, etc. are well known to those skilled in the art. Although the performance of such basic devices has been improved year by year, satisfactorily efficient processing of high-speed signals cannot be expected in the digital systems, if the wiring lines (e.g., a signal transmission line, a power supply line, a grounding line) of the circuit units actually incorporating the basic devices are left unimproved in performance.
In general, an ideal wiring structure used for the circuit units of high-speed digital systems is required to satisfy the following conditions:
(1) satisfactory control of the impedance of the signal lines;
(2) a high signal-to-noise ratio;
(3) remarkable productivity; and
(4) maintenance of high reliability during a long-term use.
Condition (1) should be satisfied, so as to prevent signal reflection and/or standing wave generation from occurring in the signal transmission lines of the circuit units. To satisfy condition (2), noise voltage which may be generated inside the circuits should be minimized, for the prevention or suppression of a current variation. To satisfy condition (3), it may be necessary to simplify the wiring pattern structure in both horizontal arrangement and sectional structure, such that the wiring pattern structure can be manufactured without involving much risk by use of the presently-available manufacturing technology. To satisfy condition (4), the wiring pattern structure that satisfies condition (3) should be formed of a material which is chemically or physically stable and which has been already proved to be fully reliable.
However, none of the wiring pattern structures which have been developed for high-speed signal processing up to now simultaneously satisfy all the conditions noted above. This is because the conditions include conflicting requirements, as will be described below.
For example, a wiring pattern structure which satisfies condition (2) is proposed in Toshiba Technical Bulletin Vol. 5-9, Apr. 1, 1987. In the wiring pattern structure of this reference, an insulated lamination structure made up of a power-supply line and a grounding (GND) line is provided around the main circuit section of a semiconductor device in such a manner that a capacitance section is formed between the power-supply line and the GND line. This capacitance section surrounds the main circuit section on the chip substrate; it serves to reduce internal noise arising from a current variation which the main circuit section undergoes in accordance with a level change in a high-speed signal. The capacitance section also serves to suppress external noise.
With this arrangement, a microstrip line path structure is employed, if it is required that high-speed signal lines traversing the capacitance section and extending to the main circuit section be provided without increasing the number of wiring layers. For instance, an upper power supply line of the peripheral capacitance section is partly formed on the lower layer to bypass a peripheral portion of the capacitance section, and high-speed signal lines are formed on the upper layer. On the lower layer of the capacitance section, therefore, the power supply line and the GND line extend in parallel to each other in the regions where the high-speed signal lines are provided. In this case, however, the impedance of the high-speed signal lines cannot be controlled in a satisfactory manner, so that condition (1) mentioned above is difficult to satisfy. In order to permit the high-speed signal lines to have desirable impedance, the material and thickness of a sandwiched insulating layer formed in the capacitance section have to be determined in such a manner as to deviate from the technical conditions presently accepted as common (i.e., a so-called "2 .mu.m rule"). In addition, the width and thickness of the high-speed signal lines may have to be determined in a similar way. If the insulating layer and the high-speed signal lines are specially designed in this fashion, it is impossible to achieve conditions (3) and (4) mentioned above.